Robust high-accuracy high-speed continuous-time CMOS current comparator

The authors present a CMOS current comparator which employs nonlinear negative feedback to obtain high-accuracy (down to 1.5pA) and high-speed for low input currents (8ns at 50nA). The new structure features a speed improvement of more than two orders of magnitude for a 1 nA input current, when compared to the fastest reported to date

A mismatch-insensitive high-accuracy high-speed continuous-time current comparator in low voltage CMOS

This paper presents a CMOS current comparator which employs nonlinear feedback to obtain high-accuracy (down to 1.5 pA) and high-speed for low input currents (8 ns@50 nA). This structure is much faster for low currents (below 10 /spl mu/A) than other previous nonlinear feedback comparators. Particularly, when compared to the fastest current comparator reported up to now, the new one operates at more that 100 times faster for a 1 nA current, with smaller area occupation and similar power consumption. In addition, the new comparator is virtually insensitive to mismatch and capable of operating with supply voltages as low as 1 V

A novel low-voltage reconfigurable ΣΔ modulator for 4G wireless receivers

This paper presents a new adaptable cascade ΣΔ modulator architecture fo r low-voltage multi-stan- dard applications. It uses two reconfiguration strategies: a programmable global resonation and a variable loop-filter order. These techniques are properly com- bined in a novel topology that allows to increase the effec- tive resolution in a given bandwidth, whereas keeping relaxed output swing requirements and high robustness to mismatch and to non-linearities of the amplifiers. Time-domain simulations incl uding the main circuit-level non-idealities are shown to demonstrate the benefits of the presented modulator when it is configured to cope with the requirements of GSM, UMTS, WLAN and Wi-Max.España, Ministerio de Educación y Ciencia TEC2007-67247-C02-01/MICEspaña, Ministerio de Innovación, Ciencia y Empresa, Junta de Andalucía TIC-253

A QVGA Vision Sensor with Multi-functional Pixels for Focal-Plane Programmable Obfuscation

Privacy awareness constitutes a critical aspect for smart camera networks. An ideal awless protection of sensitive information would boost their application scenarios. How- ever, it is still far from being achieved. Numerous chal- lenges arise at di erent levels, from hardware security to subjective perception. Generally speaking, it can be stated that the closer to the image sensing device the protection measures take place, the higher the privacy and security at- tainable. Likewise, the integration of heterogeneous camera components becomes simpler since most of them will not require to consider privacy issues. The ultimate objective would be to incorporate complete protection directly into a smart image sensor in such a way that no sensitive data would be delivered o -chip while still permitting the tar- geted video analytics. This paper presents a 320 240-px prototype vision sensor embedding processing capabilities useful for accomplishing this objective. It is based on re- con gurable focal-plane sensing-processing that can provide programmable obfuscation. Pixelation of tunable granular- ity can be applied to multiple image regions in parallel. In addition to this functionality, the sensor exploits recon g- urability to implement other processing primitives, namely block-wise high dynamic range, integral image computation and Gaussian ltering. Its power consumption ranges from 42.6mW for high dynamic range operation to 55.2mW for integral image computation at 30fps. It has been fabricated in a standard 0.18 m CMOS process.Ministerio de Economía y Competitividad TEC2012-38921-C02, IPT-2011-1625- 430000, IPC-20111009 CDTIJunta de Andalucía TIC 2338-2013Office of Naval Research (USA) N00014141035

CMOS SPADs selection, modeling and characterization towards image sensors implementation

The selection, modeling and characterization of Single Photon Avalanche Diodes (SPADs) are presented. Working with the standard 180nm UMC CMOS process, different SPAD structures are proposed in combination with several quenching circuits in order to compare their relative performances. Various configurations for the active region and the prevention of the premature edge breakdown are tested, looking for a miniaturization of the devices to implement image sensor arrays without loses in their performance

Characterization-Based Modeling of Retriggering and Afterpulsing for Passively Quenched CMOS SPADs

The current trend in the design of systems based on CMOS SPADs is to adopt smaller technological nodes, allowing the co-integration of additional electronics for the implementation of complex digital systems on chip. Due to their simplicity, a way to reduce the area occupied by the integrated electronics is the use of passive quenching circuits (PQCs) instead of active (AQCs) or mixed (MQCs) ones. However, the recharge phase in PQCs is slower, so the device can be retriggered before this phase ends. This paper studies the phenomena of afterpulsing and retriggering, depending on the characteristics of the SPADs and the working conditions. In order to do that, a test chip containing SPADs of different size has been characterized in several operating environments. A mathematical model has been proposed for fitting afterpulsing phenomenon. It is shown that retriggering can be also described in terms of this model, suggesting that it is linked to carriers trapped in the shallow levels of the semiconductor and that should be taken into account when considering the total amount of afterpulsing events.Junta de Andalucía TIC 233

Effects of capacitors non-idealities in un-even split-capacitor array SAR ADCs

This paper studies the effects of capacitors non-idealities in the performance of un-even split-capacitor SAR ADCs. Also, election of the m and l bits of MSB and LSB capacitors banks, respectively, is studied to reduce SAR errors.To exemplify and quantify the non-idealities, MOM capacitors are used. In particular, MOM layout parasitics and effective capacitor’s value is obtained with an electrical extraction tool using a flattened view of the MOM. Effects of capacitors layout placement in the SAR and their surroundings in the effective capacitance value are quantified. A quantitative study of a 10-bit un-even split-capacitor SAR is done for different combinations of m and l bits. Finally, a qualitative set of guidelines to choose the distribution of these bits is listed

Real-time single-exposure ROI-driven HDR adaptation based on focal-plane reconfiguration

Proc. SPIE 9400, Real-Time Image and Video Processing 2015This paper describes a prototype smart imager capable of adjusting the photo-integration time of multiple regions of interest concurrently, automatically and asynchronously with a single exposure period. The operation is supported by two interwined photo-diodes at pixel level and two digital registers at the periphery of the pixel matrix. These registers divide the focal-plane into independent regions within which automatic concurrent adjustment of the integration time takes place. At pixel level, one of the photo-diodes senses the pixel value itself whereas the other, in collaboration with its counterparts in a particular ROI, senses the mean illumination of that ROI. Additional circuitry interconnecting both photo-diodes enables the asynchronous adjustment of the integration time for each ROI according to this sensed illumination. The sensor can be recon gured on-the- y according to the requirements of a vision algorithm.España MINECO (FEDER) TEC2012-38921-C02 IPT-2011-1625-430000 IPC-20111009 CDTIJunta de Andalucía TIC 2338-2013 CEIC

Design of a power-efficient widely-programmable Gm-LC band-pass sigma-delta modulator for SDR

This paper presents the design and implementation of a fourth-order band-pass continuous-time modulator intended for the digitization of radio-frequency signals in softwaredefined- radio applications. The modulator architecture consists of two Gm-LC resonators with a tunable notch frequency and a 4-bit flash analog-to-digital converter in the forward path and a non-return-to-zero digital-to-analog converter with a finiteimpulse- response filter in the feedback path. Both system-level and circuit-level reconfiguration techniques are included in order to allow the modulator to digitize signals placed at different carrier frequencies, from 450MHz to 950MHz. A proper synthesis methodology of the loop-filter coefficients at system level and the use of inverter-based switchable transconductors allow to optimize the performance in terms of robustness to circuit errors, stability and power consumption. The circuit, implemented in 65- nm CMOS, can digitise signals with up to 57-dB SNDR within a 40-MHz bandwidth, with an adaptive power dissipation of 16.7- to-22.8 mW and a programmable 1.2/2GHz clock rate1

Design of a 130-nm CMOS Reconfigurable Cascade ΣΔ Modulator for GSM/UMTS/Bluetooth

This paper reports a 130-nm CMOS programmable cascade ΣΔ modulator for multistandard wireless terminals, covering three standards: GSM, Bluetooth and UMTS. The modulator is reconfigured at both architecture- and circuitlevel in order to adapt its performance to the different standard specifications with optimized power consumption. The design of the building blocks is based upon a top-down CAD methodology that combines simulation and statistical optimization at different levels of the system hierarchy. Transistor-level simulations show correct operation for all standards, featuring 13-bit, 11.3-bit and 9-bit effective resolution within 200-kHz, 1-MHz and 4-MHz bandwidth, respectively.España, Ministerio de Educación y Ciencia TEC2004-01752/MI